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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-07-26 18:12:36 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-07-26 18:12:36 -0700 |
commit | b357c97b249cdb13cc08f0893d73994662b5be8d (patch) | |
tree | 4945a8f9088735c025b02d11abfd21bf83260d7f /riscv | |
parent | bda232b0117adbc949b87ffb71fda34e51c891bc (diff) | |
download | riscv-isa-sim-b357c97b249cdb13cc08f0893d73994662b5be8d.zip riscv-isa-sim-b357c97b249cdb13cc08f0893d73994662b5be8d.tar.gz riscv-isa-sim-b357c97b249cdb13cc08f0893d73994662b5be8d.tar.bz2 |
Remove more vector stuff
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/decode.h | 63 | ||||
-rw-r--r-- | riscv/mmu.h | 3 | ||||
-rw-r--r-- | riscv/processor.cc | 51 | ||||
-rw-r--r-- | riscv/processor.h | 21 | ||||
-rw-r--r-- | riscv/riscv.ac | 10 |
5 files changed, 5 insertions, 143 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 7c99581..1dfec6e 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -166,10 +166,6 @@ private: T data[N]; }; -#define throw_illegal_instruction \ - ({ if (utmode) throw trap_vector_illegal_instruction; \ - else throw trap_illegal_instruction; }) - // helpful macros, etc #define RS1 XPR[insn.rtype.rs1] #define RS2 XPR[insn.rtype.rs2] @@ -191,27 +187,19 @@ private: #define BTYPE_EADDR sext_xprlen(RS1 + BIMM) #define RM ({ int rm = insn.ftype.rm; \ if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \ - if(rm > 4) throw_illegal_instruction; \ + if(rm > 4) throw trap_illegal_instruction; \ rm; }) #define xpr64 (xprlen == 64) #define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction -#define require_xpr64 if(unlikely(!xpr64)) throw_illegal_instruction -#define require_xpr32 if(unlikely(xpr64)) throw_illegal_instruction +#define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction +#define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction #ifndef RISCV_ENABLE_FPU # define require_fp throw trap_illegal_instruction #else # define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled #endif -#ifndef RISCV_ENABLE_VEC -# define require_vector throw trap_illegal_instruction -#else -# define require_vector \ - ({ if(!(sr & SR_EV)) throw trap_vector_disabled; \ - else if (!utmode && (vecbanks_count < 3)) throw trap_vector_bank; \ - }) -#endif #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen)) #define set_fp_exceptions ({ set_fsr(fsr | \ @@ -235,49 +223,4 @@ private: npc = (x); \ } while(0) -// vector stuff -#define VL vl - -#define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1] -#define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2] -#define UT_RD(idx) uts[idx]->XPR.write_port(insn.rtype.rd) -#define UT_RA(idx) uts[idx]->XPR.write_port(1) -#define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1] -#define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2] -#define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3] -#define UT_FRD(idx) uts[idx]->FPR.write_port(insn.ftype.rd) -#define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \ - ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT)) - -#define UT_LOOP_START for (int i=0;i<VL; i++) { -#define UT_LOOP_END } -#define UT_LOOP_RS1 UT_RS1(i) -#define UT_LOOP_RS2 UT_RS2(i) -#define UT_LOOP_RD UT_RD(i) -#define UT_LOOP_RA UT_RA(i) -#define UT_LOOP_FRS1 UT_FRS1(i) -#define UT_LOOP_FRS2 UT_FRS2(i) -#define UT_LOOP_FRS3 UT_FRS3(i) -#define UT_LOOP_FRD UT_FRD(i) -#define UT_LOOP_RM UT_RM(i) - -#define VEC_LOAD(dst, func, inc) \ - reg_t addr = RS1; \ - UT_LOOP_START \ - UT_LOOP_##dst = mmu.func(addr); \ - addr += inc; \ - UT_LOOP_END - -#define VEC_STORE(src, func, inc) \ - reg_t addr = RS1; \ - UT_LOOP_START \ - mmu.func(addr, UT_LOOP_##src); \ - addr += inc; \ - UT_LOOP_END - -enum vt_command_t -{ - vt_command_stop, -}; - #endif diff --git a/riscv/mmu.h b/riscv/mmu.h index 49a5f0b..64b11d3 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -104,9 +104,6 @@ public: // load instruction from memory at aligned address. inline insn_fetch_t load_insn(reg_t addr) { -#ifdef RISCV_ENABLE_RVC -# error TODO: Make MMU instruction cache support 2-byte alignment -#endif reg_t idx = (addr/sizeof(insn_t::itype)) % ICACHE_ENTRIES; if (unlikely(icache_tag[idx] != addr)) { diff --git a/riscv/processor.cc b/riscv/processor.cc index 42182bd..e7c0872 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -13,7 +13,7 @@ #include <limits.h> processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id) - : sim(*_sim), mmu(*_mmu), id(_id), opcode_bits(0), utidx(0) + : sim(*_sim), mmu(*_mmu), id(_id), opcode_bits(0) { reset(true); mmu.set_processor(this); @@ -22,23 +22,6 @@ processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id) register_insn(match, mask, (insn_func_t)&processor_t::rv32_##name, (insn_func_t)&processor_t::rv64_##name); #include "opcodes.h" #undef DECLARE_INSN - - // create microthreads - for (int i=0; i<MAX_UTS; i++) - uts[i] = new processor_t(&sim, &mmu, id, i); -} - -processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id, - uint32_t _utidx) - : sim(*_sim), mmu(*_mmu), id(_id) -{ - reset(true); - set_pcr(PCR_SR, SR_U64 | SR_EF | SR_EV); - utidx = _utidx; - - // microthreads don't possess their own microthreads - for (int i=0; i<MAX_UTS; i++) - uts[i] = NULL; } processor_t::~processor_t() @@ -73,16 +56,6 @@ void processor_t::reset(bool value) compare = 0; cycle = 0; set_fsr(0); - - // vector stuff - vecbanks = 0xff; - vecbanks_count = 8; - utidx = -1; - vlmax = 32; - vl = 0; - nxfpr_bank = 256; - nxpr_use = 32; - nfpr_use = 32; } void processor_t::set_fsr(uint32_t val) @@ -90,21 +63,6 @@ void processor_t::set_fsr(uint32_t val) fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero } -void processor_t::vcfg() -{ - if (nxpr_use + nfpr_use < 2) - vlmax = nxfpr_bank * vecbanks_count; - else - vlmax = (nxfpr_bank / (nxpr_use + nfpr_use - 1)) * vecbanks_count; - - vlmax = std::min(vlmax, MAX_UTS); -} - -void processor_t::setvl(int vlapp) -{ - vl = std::min(vlmax, vlapp); -} - void processor_t::take_interrupt() { uint32_t interrupts = (sr & SR_IP) >> SR_IP_SHIFT; @@ -161,12 +119,7 @@ void processor_t::step(size_t n, bool noisy) } catch(interrupt_t t) { - take_trap((1ULL << (8*sizeof(reg_t)-1)) + t.i, noisy); - } - catch(vt_command_t cmd) - { - // this microthread has finished - assert(cmd == vt_command_stop); + take_trap((1ULL << ((sr & SR_S64) ? 63 : 31)) + t.i, noisy); } cycle += i; diff --git a/riscv/processor.h b/riscv/processor.h index 08c3672..e21901c 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -9,8 +9,6 @@ #include "config.h" #include <map> -#define MAX_UTS 2048 - class processor_t; class mmu_t; typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t); @@ -76,25 +74,6 @@ private: void take_trap(reg_t t, bool noisy); // take an exception void disasm(insn_t insn, reg_t pc); // disassemble and print an instruction - // vector stuff - void vcfg(); - void setvl(int vlapp); - - reg_t vecbanks; - uint32_t vecbanks_count; - - bool utmode; - uint32_t utidx; - int vlmax; - int vl; - int nxfpr_bank; - int nxpr_use; - int nfpr_use; - processor_t* uts[MAX_UTS]; - - // this constructor is used for each of the uts - processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id, uint32_t _utidx); - friend class sim_t; friend class mmu_t; friend class htif_isasim_t; diff --git a/riscv/riscv.ac b/riscv/riscv.ac index 687d5bc..335a0bf 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -20,13 +20,3 @@ AC_ARG_ENABLE([64bit], AS_HELP_STRING([--disable-64bit], [Disable 64-bit mode])) AS_IF([test "x$enable_64bit" != "xno"], [ AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported]) ]) - -AC_ARG_ENABLE([rvc], AS_HELP_STRING([--enable-rvc], [Enable instruction compression])) -AS_IF([test "x$enable_rvc" = "xyes"], [ - AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported]) -]) - -AC_ARG_ENABLE([vec], AS_HELP_STRING([--disable-vec], [Disable vector processor])) -AS_IF([test "x$enable_vec" != "xno"], [ - AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported]) -]) |