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author | Quan Nguyen <quannguyen@berkeley.edu> | 2013-07-31 21:33:25 -0700 |
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committer | Quan Nguyen <quannguyen@berkeley.edu> | 2013-07-31 21:37:44 -0700 |
commit | a39658bf83c03c734fef210131d649540940258a (patch) | |
tree | 7363601984c7d2033554b3eb91f0dc33230384b7 /riscv | |
parent | 7a05cbde1789c7cf65b9c2b03c9529ab99dc97e6 (diff) | |
download | riscv-isa-sim-a39658bf83c03c734fef210131d649540940258a.zip riscv-isa-sim-a39658bf83c03c734fef210131d649540940258a.tar.gz riscv-isa-sim-a39658bf83c03c734fef210131d649540940258a.tar.bz2 |
Fix eret (again)
* Set SR_S if SR_PS is set, not the other way around
(that is, set SR_S if SR_PS is not set).
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/insns/eret.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/eret.h b/riscv/insns/eret.h index deed103..9ea8baf 100644 --- a/riscv/insns/eret.h +++ b/riscv/insns/eret.h @@ -1,5 +1,5 @@ require_supervisor; set_pcr(PCR_SR, ((sr & ~(SR_S | SR_EI)) | - ((sr & SR_PS) ? 0 : SR_S)) | + ((sr & SR_PS) ? SR_S : 0)) | ((sr & SR_PEI) ? SR_EI : 0)); set_pc(epc); |