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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-03-29 18:26:07 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-03-29 18:26:07 -0700 |
| commit | 983a062e287ebe0d69c17448e67da6223cf48080 (patch) | |
| tree | 55cc5780a13e721705b38584552545d9e6eaa2b3 /riscv | |
| parent | 93229b56ba4d7d63523eb57f05394f8b81e0df2a (diff) | |
| download | riscv-isa-sim-983a062e287ebe0d69c17448e67da6223cf48080.zip riscv-isa-sim-983a062e287ebe0d69c17448e67da6223cf48080.tar.gz riscv-isa-sim-983a062e287ebe0d69c17448e67da6223cf48080.tar.bz2 | |
ignore writes to SR IP field
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/processor.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index dbae921..ba65a93 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -47,6 +47,7 @@ void processor_t::reset(bool value) // the ISA guarantees on boot that the PC is 0x2000 and the the processor // is in supervisor mode, and in 64-bit mode, if supported, with traps // and virtual memory disabled. + sr = 0; set_pcr(PCR_SR, SR_S | SR_S64 | SR_IM); pc = 0x2000; @@ -209,7 +210,7 @@ void processor_t::set_pcr(int which, reg_t val) switch (which) { case PCR_SR: - sr = val & ~SR_ZERO; // clear SR bits that read as zero + sr = (val & ~SR_IP) | (sr & SR_IP); #ifndef RISCV_ENABLE_64BIT sr &= ~(SR_S64 | SR_U64); #endif @@ -222,7 +223,7 @@ void processor_t::set_pcr(int which, reg_t val) #ifndef RISCV_ENABLE_VEC sr &= ~SR_EV; #endif - // update MMU state and flush TLB + sr &= ~SR_ZERO; mmu.set_sr(sr); mmu.flush_tlb(); // set the fixed-point register length |