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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-07-12 18:20:16 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-07-12 18:23:55 -0700 |
| commit | 6de0c1e324745f426d5ff3c30af2acbe10042ceb (patch) | |
| tree | b0bee7d26ee18e6219e83f5c3f22a2aec9c1fbb2 /riscv | |
| parent | 34be1b9afd19f2c8a509922c8bf2fd12ebb46e4b (diff) | |
| download | riscv-isa-sim-6de0c1e324745f426d5ff3c30af2acbe10042ceb.zip riscv-isa-sim-6de0c1e324745f426d5ff3c30af2acbe10042ceb.tar.gz riscv-isa-sim-6de0c1e324745f426d5ff3c30af2acbe10042ceb.tar.bz2 | |
Fix SR_U64 bit being ignored
Diffstat (limited to 'riscv')
| -rwxr-xr-x | riscv/dispatch | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/dispatch b/riscv/dispatch index 231853c..5afc3be 100755 --- a/riscv/dispatch +++ b/riscv/dispatch @@ -49,7 +49,7 @@ if filenum == numfiles: if filenum == numfiles+1: print '#define get_insn_func(insn, sr) \\' - print ' processor_t::dispatch_table[((((sr) & SR_S) ? (sr & SR_S64) : (SR_U64)) ? %d : 0) + ((insn).bits %% %d)]' % (tablesz, tablesz) + print ' processor_t::dispatch_table[((((sr) & SR_S) ? (sr & SR_S64) : (sr & SR_U64)) ? %d : 0) + ((insn).bits %% %d)]' % (tablesz, tablesz) print 'static const insn_func_t dispatch_table[%d];' % (2*tablesz) for i in range(0, tablesz): |