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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-04-24 01:46:16 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-04-24 01:46:16 -0700 |
| commit | 4944ab3c0296f906549d7eb3417fbaa771e476fe (patch) | |
| tree | 7aa736feff75df8ce63fd6f4124b6eecb907598a /riscv | |
| parent | 789abb77fb313b688f83bc292453b1f127188ff0 (diff) | |
| download | riscv-isa-sim-4944ab3c0296f906549d7eb3417fbaa771e476fe.zip riscv-isa-sim-4944ab3c0296f906549d7eb3417fbaa771e476fe.tar.gz riscv-isa-sim-4944ab3c0296f906549d7eb3417fbaa771e476fe.tar.bz2 | |
fixes to correctly simulate the vector unit
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/decode.h | 2 | ||||
| -rw-r--r-- | riscv/processor.cc | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index bf16e72..3ef8864 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -152,6 +152,8 @@ public: } write_port_t<T> write_port(size_t i) { + if (zero_reg) + const_cast<T&>(data[0]) = 0; return write_port_t<T>(data[i]); } const T& operator [] (size_t i) const diff --git a/riscv/processor.cc b/riscv/processor.cc index 39a9ec0..e124820 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -299,6 +299,8 @@ reg_t processor_t::get_pcr(int which) return pcr_k1; case PCR_VECBANK: return vecbanks; + case PCR_VECCFG: + return nfpr_use << 18 | nxpr_use << 12 | vl; case PCR_TOHOST: return tohost; case PCR_FROMHOST: |