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authorAndrew Waterman <waterman@eecs.berkeley.edu>2014-01-21 16:20:58 -0800
committerAndrew Waterman <waterman@eecs.berkeley.edu>2014-01-21 16:21:17 -0800
commit2fa668a2d0a58165781ebec4f8e64e7a84fd4f6a (patch)
tree9d5be363ac1b8660665badba1ace822e96a9475c /riscv
parentbd9a5a429dad8ab54ae28d783eea6c3d7b6905f3 (diff)
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Use auto-generated trap cause numbers
Diffstat (limited to 'riscv')
-rw-r--r--riscv/encoding.h53
-rw-r--r--riscv/trap.h25
2 files changed, 52 insertions, 26 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h
index 711ef7b..4ee6e68 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -26,19 +26,6 @@
#define IMPL_SPIKE 1
#define IMPL_ROCKET 2
-#define CAUSE_MISALIGNED_FETCH 0
-#define CAUSE_FAULT_FETCH 1
-#define CAUSE_ILLEGAL_INSTRUCTION 2
-#define CAUSE_PRIVILEGED_INSTRUCTION 3
-#define CAUSE_FP_DISABLED 4
-#define CAUSE_SYSCALL 6
-#define CAUSE_BREAKPOINT 7
-#define CAUSE_MISALIGNED_LOAD 8
-#define CAUSE_MISALIGNED_STORE 9
-#define CAUSE_FAULT_LOAD 10
-#define CAUSE_FAULT_STORE 11
-#define CAUSE_ACCELERATOR_DISABLED 12
-
// page table entry (PTE) fields
#define PTE_V 0x001 // Entry is a page Table descriptor
#define PTE_T 0x002 // Entry is a page Table, not a terminal node
@@ -438,6 +425,18 @@
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FAULT_FETCH 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_PRIVILEGED_INSTRUCTION 0x3
+#define CAUSE_FP_DISABLED 0x4
+#define CAUSE_SYSCALL 0x6
+#define CAUSE_BREAKPOINT 0x7
+#define CAUSE_MISALIGNED_LOAD 0x8
+#define CAUSE_MISALIGNED_STORE 0x9
+#define CAUSE_FAULT_LOAD 0xa
+#define CAUSE_FAULT_STORE 0xb
+#define CAUSE_ACCELERATOR_DISABLED 0xc
#endif
#ifdef DECLARE_INSN
DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
@@ -624,3 +623,31 @@ DECLARE_CSR(cycle, CSR_CYCLE)
DECLARE_CSR(time, CSR_TIME)
DECLARE_CSR(instret, CSR_INSTRET)
#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
+DECLARE_CAUSE("frm", CAUSE_FRM)
+DECLARE_CAUSE("fcsr", CAUSE_FCSR)
+DECLARE_CAUSE("sup0", CAUSE_SUP0)
+DECLARE_CAUSE("sup1", CAUSE_SUP1)
+DECLARE_CAUSE("epc", CAUSE_EPC)
+DECLARE_CAUSE("badvaddr", CAUSE_BADVADDR)
+DECLARE_CAUSE("ptbr", CAUSE_PTBR)
+DECLARE_CAUSE("asid", CAUSE_ASID)
+DECLARE_CAUSE("count", CAUSE_COUNT)
+DECLARE_CAUSE("compare", CAUSE_COMPARE)
+DECLARE_CAUSE("evec", CAUSE_EVEC)
+DECLARE_CAUSE("cause", CAUSE_CAUSE)
+DECLARE_CAUSE("status", CAUSE_STATUS)
+DECLARE_CAUSE("hartid", CAUSE_HARTID)
+DECLARE_CAUSE("impl", CAUSE_IMPL)
+DECLARE_CAUSE("fatc", CAUSE_FATC)
+DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
+DECLARE_CAUSE("clear_ipi", CAUSE_CLEAR_IPI)
+DECLARE_CAUSE("stats", CAUSE_STATS)
+DECLARE_CAUSE("reset", CAUSE_RESET)
+DECLARE_CAUSE("tohost", CAUSE_TOHOST)
+DECLARE_CAUSE("fromhost", CAUSE_FROMHOST)
+DECLARE_CAUSE("cycle", CAUSE_CYCLE)
+DECLARE_CAUSE("time", CAUSE_TIME)
+DECLARE_CAUSE("instret", CAUSE_INSTRET)
+#endif
diff --git a/riscv/trap.h b/riscv/trap.h
index bd7e0ee..6e80a7c 100644
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -42,18 +42,17 @@ class mem_trap_t : public trap_t
const char* name() { return "trap_"#x; } \
};
-DECLARE_TRAP(0, instruction_address_misaligned)
-DECLARE_TRAP(1, instruction_access_fault)
-DECLARE_TRAP(2, illegal_instruction)
-DECLARE_TRAP(3, privileged_instruction)
-DECLARE_TRAP(4, fp_disabled)
-DECLARE_TRAP(5, reserved0)
-DECLARE_TRAP(6, syscall)
-DECLARE_TRAP(7, breakpoint)
-DECLARE_MEM_TRAP(8, load_address_misaligned)
-DECLARE_MEM_TRAP(9, store_address_misaligned)
-DECLARE_MEM_TRAP(10, load_access_fault)
-DECLARE_MEM_TRAP(11, store_access_fault)
-DECLARE_TRAP(12, accelerator_disabled)
+DECLARE_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
+DECLARE_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault)
+DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
+DECLARE_TRAP(CAUSE_PRIVILEGED_INSTRUCTION, privileged_instruction)
+DECLARE_TRAP(CAUSE_FP_DISABLED, fp_disabled)
+DECLARE_TRAP(CAUSE_SYSCALL, syscall)
+DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint)
+DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned)
+DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned)
+DECLARE_MEM_TRAP(CAUSE_FAULT_LOAD, load_access_fault)
+DECLARE_MEM_TRAP(CAUSE_FAULT_STORE, store_access_fault)
+DECLARE_TRAP(CAUSE_ACCELERATOR_DISABLED, accelerator_disabled)
#endif