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author | Christopher Celio <celio@eecs.berkeley.edu> | 2014-08-15 15:38:41 -0700 |
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committer | Christopher Celio <celio@eecs.berkeley.edu> | 2014-08-15 15:38:41 -0700 |
commit | 616cc32c30ac0684edfd50ed44fc78ed1bc20884 (patch) | |
tree | 3ad9cbea79da5a40a5a351e842e1e890a07ad298 /riscv/sim.h | |
parent | e2c0c3021ac2fa7cad5866e0f100c2dbf2372986 (diff) | |
download | riscv-isa-sim-616cc32c30ac0684edfd50ed44fc78ed1bc20884.zip riscv-isa-sim-616cc32c30ac0684edfd50ed44fc78ed1bc20884.tar.gz riscv-isa-sim-616cc32c30ac0684edfd50ed44fc78ed1bc20884.tar.bz2 |
Added PC histogram option.
- Spits out all PCs (on 4B granularity) executed with count.
- Requires a compile time configuration option.
- Also requires a run-time flag.
Diffstat (limited to 'riscv/sim.h')
-rw-r--r-- | riscv/sim.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index d437c1a..9e1362e 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -23,6 +23,7 @@ public: bool running(); void stop(); void set_debug(bool value); + void set_histogram(bool value); void set_procs_debug(bool value); htif_isasim_t* get_htif() { return htif.get(); } @@ -48,6 +49,7 @@ private: size_t current_step; size_t current_proc; bool debug; + bool histogram_enabled; // provide a histogram of PCs // presents a prompt for introspection into the simulation void interactive(); |