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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-27 00:52:59 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-28 22:36:14 -0700 |
| commit | f5983b39c583971b8443b9f16705cbfb1588dbf5 (patch) | |
| tree | 7253b1326823f05f051060a9e36bfe9635d0d9f3 /riscv/riscv.mk.in | |
| parent | fb84a685a89603eb91bd36261addc0fd13d2b576 (diff) | |
| download | riscv-isa-sim-f5983b39c583971b8443b9f16705cbfb1588dbf5.zip riscv-isa-sim-f5983b39c583971b8443b9f16705cbfb1588dbf5.tar.gz riscv-isa-sim-f5983b39c583971b8443b9f16705cbfb1588dbf5.tar.bz2 | |
rvv: add new singed/unsiged extension instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index fbe6786..cbb6088 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -442,6 +442,9 @@ riscv_insn_ext_v_alu_int = \ vsaddu_vx \ vsbc_vvm \ vsbc_vxm \ + vsext_vf2 \ + vsext_vf4 \ + vsext_vf8 \ vslide1down_vx \ vslide1up_vx \ vslidedown_vi \ @@ -505,6 +508,9 @@ riscv_insn_ext_v_alu_int = \ vxor_vi \ vxor_vv \ vxor_vx \ + vzext_vf2 \ + vzext_vf4 \ + vzext_vf8 \ riscv_insn_ext_v_alu_fp = \ vfadd_vf \ |