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| author | Tim Newsome <tim@sifive.com> | 2022-03-15 07:57:51 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-03-30 10:30:53 -0700 |
| commit | 273fa05167c873e2cc92862ddbb52b10806f439a (patch) | |
| tree | a9168b290d829fffec933632085565e8a9a9e2a9 /riscv/riscv.mk.in | |
| parent | 3bbaab01762f0b5bac1fd816370c270ffe28fd6b (diff) | |
| download | riscv-isa-sim-273fa05167c873e2cc92862ddbb52b10806f439a.zip riscv-isa-sim-273fa05167c873e2cc92862ddbb52b10806f439a.tar.gz riscv-isa-sim-273fa05167c873e2cc92862ddbb52b10806f439a.tar.bz2 | |
Create triggers.cc, triggers.h.
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index ecbda5d..0c6b977 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -32,6 +32,7 @@ riscv_hdrs = \ remote_bitbang.h \ jtag_dtm.h \ csrs.h \ + triggers.h \ riscv_install_hdrs = mmio_plugin.h @@ -57,6 +58,7 @@ riscv_srcs = \ remote_bitbang.cc \ jtag_dtm.cc \ csrs.cc \ + triggers.cc \ $(riscv_gen_srcs) \ riscv_test_srcs = |