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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-08-13 00:51:07 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-08-13 00:51:07 -0700 |
| commit | bbb0f2179c858c77918ef37dbfcd7bb5f3fd0417 (patch) | |
| tree | 63bcac40261140f5628d1e12182d658005eae300 /riscv/riscv.mk.in | |
| parent | 04c2d491c4bbb424a59273d4ebee62ddfe3379f9 (diff) | |
| download | riscv-isa-sim-bbb0f2179c858c77918ef37dbfcd7bb5f3fd0417.zip riscv-isa-sim-bbb0f2179c858c77918ef37dbfcd7bb5f3fd0417.tar.gz riscv-isa-sim-bbb0f2179c858c77918ef37dbfcd7bb5f3fd0417.tar.bz2 | |
Implement RoCC and add a dummy RoCC
Enable it with --extension=dummy
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index b9030db..781a1a3 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -21,6 +21,9 @@ riscv_hdrs = \ opcodes.h \ cachesim.h \ memtracer.h \ + extension.h \ + rocc.h \ + dummy-rocc.h \ riscv_srcs = \ htif.cc \ @@ -31,6 +34,8 @@ riscv_srcs = \ cachesim.cc \ mmu.cc \ disasm.cc \ + extension.cc \ + rocc.cc \ $(riscv_gen_srcs) \ riscv_test_srcs = |