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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-29 13:58:19 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-12-29 13:58:19 -0800 |
| commit | e4126acfa47f7a7cb463a86782aa2dcef0796608 (patch) | |
| tree | 07bc5a476d1dbb8ed160bf7e600e8b983deea117 /riscv/processor.h | |
| parent | f11c7b64b488a64a613bbc4ba02f83e929998d14 (diff) | |
| download | riscv-isa-sim-e4126acfa47f7a7cb463a86782aa2dcef0796608.zip riscv-isa-sim-e4126acfa47f7a7cb463a86782aa2dcef0796608.tar.gz riscv-isa-sim-e4126acfa47f7a7cb463a86782aa2dcef0796608.tar.bz2 | |
Make obvious that PC alignment mask is a function of IALIGN
No functional change.
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index f65faf6..86d89fb 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -236,7 +236,8 @@ public: return impl_table[impl]; } reg_t pc_alignment_mask() { - return ~(reg_t)(extension_enabled(EXT_ZCA) ? 0 : 2); + const int ialign = extension_enabled(EXT_ZCA) ? 16 : 32; + return ~(reg_t)(ialign == 16 ? 0 : 2); } void check_pc_alignment(reg_t pc) { if (unlikely(pc & ~pc_alignment_mask())) |