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| author | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-29 14:59:55 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-29 14:59:55 -0700 |
| commit | 9ac2dcf9a58846179d93eaebfe8f3b1b30f1d280 (patch) | |
| tree | cbf10b326c4368c5dc64370c7822a65d62e02343 /riscv/processor.h | |
| parent | 88c1bfce90a12f11ab8bc53659535afe618d7f3b (diff) | |
| download | riscv-isa-sim-9ac2dcf9a58846179d93eaebfe8f3b1b30f1d280.zip riscv-isa-sim-9ac2dcf9a58846179d93eaebfe8f3b1b30f1d280.tar.gz riscv-isa-sim-9ac2dcf9a58846179d93eaebfe8f3b1b30f1d280.tar.bz2 | |
Convert vtype to csr_t
Adds commit log events for vtype to many vector instructions.
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index c4a4243..3fcdcfd 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -511,8 +511,8 @@ public: char reg_referenced[NVPR]; int setvl_count; reg_t vlmax; - reg_t vtype, vlenb; - vector_csr_t_p vxrm, vstart, vxsat, vl; + reg_t vlenb; + vector_csr_t_p vxrm, vstart, vxsat, vl, vtype; reg_t vma, vta; reg_t vsew; float vflmul; @@ -553,12 +553,12 @@ public: reg_referenced{0}, setvl_count(0), vlmax(0), - vtype(0), vlenb(0), vxrm(0), vstart(0), vxsat(0), vl(0), + vtype(0), vma(0), vta(0), vsew(0), |