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| author | Tim Newsome <tim@sifive.com> | 2022-03-24 11:30:07 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-04-05 10:33:31 -0700 |
| commit | 825b396c4dba96f9941fdc4a38301e890c8c9d12 (patch) | |
| tree | da50ffe592de3d39513b3f09de4492a0c701e67d /riscv/processor.h | |
| parent | 972943662c6e608e5d321c9128cdb9aaf903a4ae (diff) | |
| download | riscv-isa-sim-825b396c4dba96f9941fdc4a38301e890c8c9d12.zip riscv-isa-sim-825b396c4dba96f9941fdc4a38301e890c8c9d12.tar.gz riscv-isa-sim-825b396c4dba96f9941fdc4a38301e890c8c9d12.tar.bz2 | |
Move num_triggers knowledge into triggers.h
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 776496c..a09b6b6 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -124,8 +124,6 @@ struct state_t { void reset(processor_t* const proc, reg_t max_isa); - static const int num_triggers = 4; - reg_t pc; regfile_t<reg_t, NXPR, true> XPR; regfile_t<freg_t, NFPR, false> FPR; |