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| author | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-20 14:31:03 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-25 23:50:53 -0700 |
| commit | 53f810cd744b5ce912415038791eaee2836eec6f (patch) | |
| tree | e682487fac9da5e5f85fe4a5f6ec382e85257704 /riscv/processor.h | |
| parent | ef6366e27a96609e538f762c80a334a118d377ce (diff) | |
| download | riscv-isa-sim-53f810cd744b5ce912415038791eaee2836eec6f.zip riscv-isa-sim-53f810cd744b5ce912415038791eaee2836eec6f.tar.gz riscv-isa-sim-53f810cd744b5ce912415038791eaee2836eec6f.tar.bz2 | |
Convert hideleg to csr_t
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index c1b70bf..b34df1d 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -187,7 +187,7 @@ struct state_t csr_t_p mtval2; csr_t_p mtinst; csr_t_p hstatus; - reg_t hideleg; + csr_t_p hideleg; csr_t_p hedeleg; csr_t_p hcounteren; csr_t_p htval; |