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| author | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-29 09:30:42 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-29 14:08:35 -0700 |
| commit | 347ff31125bee0fadd8e02bbe7a13c672dcf74a5 (patch) | |
| tree | ad6077ca4914f00b1de70f422dbaf3442f1fd2fe /riscv/processor.h | |
| parent | 52c23a28c519449a874cd7ea2ec0479b63a3b173 (diff) | |
| download | riscv-isa-sim-347ff31125bee0fadd8e02bbe7a13c672dcf74a5.zip riscv-isa-sim-347ff31125bee0fadd8e02bbe7a13c672dcf74a5.tar.gz riscv-isa-sim-347ff31125bee0fadd8e02bbe7a13c672dcf74a5.tar.bz2 | |
Convert vxsat to csr_t
Adds commit log events for vxsat to many vector instructions.
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 19579f0..dc8c987 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -511,7 +511,8 @@ public: char reg_referenced[NVPR]; int setvl_count; reg_t vlmax; - reg_t vstart, vxrm, vxsat, vl, vtype, vlenb; + reg_t vstart, vxrm, vl, vtype, vlenb; + csr_t_p vxsat; reg_t vma, vta; reg_t vsew; float vflmul; @@ -554,10 +555,10 @@ public: vlmax(0), vstart(0), vxrm(0), - vxsat(0), vl(0), vtype(0), vlenb(0), + vxsat(0), vma(0), vta(0), vsew(0), |