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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-06-28 10:38:40 +0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-11-17 16:40:00 -0800 |
| commit | 087626c280571b13e5ee51a3a7603c8bbd96916a (patch) | |
| tree | 5c630c7ff388d119bf9ef68221a38b9679f824aa /riscv/processor.h | |
| parent | 1160ea7f1b1026884bef3b8ac2caf613c8e9a475 (diff) | |
| download | riscv-isa-sim-087626c280571b13e5ee51a3a7603c8bbd96916a.zip riscv-isa-sim-087626c280571b13e5ee51a3a7603c8bbd96916a.tar.gz riscv-isa-sim-087626c280571b13e5ee51a3a7603c8bbd96916a.tar.bz2 | |
add support for zcmt
add suport for jvt: Table entries follow the current data endianness
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index a660399..e531852 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -175,6 +175,9 @@ struct state_t dcsr_csr_t_p dcsr; csr_t_p tselect; tdata2_csr_t_p tdata2; + + csr_t_p jvt; + bool debug_mode; mseccfg_csr_t_p mseccfg; |