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| author | Andrew Waterman <andrew@sifive.com> | 2023-11-15 16:42:07 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-11-15 16:42:07 -0800 |
| commit | 61d54d0e07d96a2b6bb9e4cb9b8c5ae9260be3de (patch) | |
| tree | 24ed6c62b3abe975e475f7feccb228af89fd4c1d /riscv/processor.cc | |
| parent | be5dee0bafb413c9ac8845ca144db9b7641941b2 (diff) | |
| download | riscv-isa-sim-61d54d0e07d96a2b6bb9e4cb9b8c5ae9260be3de.zip riscv-isa-sim-61d54d0e07d96a2b6bb9e4cb9b8c5ae9260be3de.tar.gz riscv-isa-sim-61d54d0e07d96a2b6bb9e4cb9b8c5ae9260be3de.tar.bz2 | |
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 0ac6e67..469da1e 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -611,6 +611,9 @@ void processor_t::set_histogram(bool value) void processor_t::enable_log_commits() { log_commits_enabled = true; + + // commit logging occurs on the TLB-miss path + mmu->flush_tlb(); } void processor_t::reset() |