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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-01-18 17:51:52 -0800 |
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| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-01-18 17:51:52 -0800 |
| commit | 21ce327f5d60d6805b5d9328b68f7ad2c261a859 (patch) | |
| tree | 22ee7ac3dfb4d00662ff6f0d1f057481efc67772 /riscv/insns/mulw.h | |
| parent | 5ddec097b858aafe783eb3aff551d00e9c8c8a37 (diff) | |
| download | riscv-isa-sim-21ce327f5d60d6805b5d9328b68f7ad2c261a859.zip riscv-isa-sim-21ce327f5d60d6805b5d9328b68f7ad2c261a859.tar.gz riscv-isa-sim-21ce327f5d60d6805b5d9328b68f7ad2c261a859.tar.bz2 | |
[opcodes, sim, xcc] made *w insns illegal in RV32
now generic variants behave differently in RV32 and RV64.
Diffstat (limited to 'riscv/insns/mulw.h')
| -rw-r--r-- | riscv/insns/mulw.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h index 81285a2..7b0a934 100644 --- a/riscv/insns/mulw.h +++ b/riscv/insns/mulw.h @@ -1,2 +1,2 @@ +require_xpr64; RD = sext32(RS1 * RS2); - |