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| author | Tim Newsome <tim@sifive.com> | 2016-05-02 18:07:51 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | fdc92ba2c5ad75abf1e86c87ea23fb7d7dd00ca1 (patch) | |
| tree | ba46567c0ffcc37f0fd3e3e46217f51e071ba6ad /riscv/insns/dret.h | |
| parent | 19f33802a18c23765515324167276b2a47ec8e22 (diff) | |
| download | riscv-isa-sim-fdc92ba2c5ad75abf1e86c87ea23fb7d7dd00ca1.zip riscv-isa-sim-fdc92ba2c5ad75abf1e86c87ea23fb7d7dd00ca1.tar.gz riscv-isa-sim-fdc92ba2c5ad75abf1e86c87ea23fb7d7dd00ca1.tar.bz2 | |
Add dret.
Diffstat (limited to 'riscv/insns/dret.h')
| -rw-r--r-- | riscv/insns/dret.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h new file mode 100644 index 0000000..6cfd1e2 --- /dev/null +++ b/riscv/insns/dret.h @@ -0,0 +1,6 @@ +require_privilege(PRV_M); +set_pc_and_serialize(STATE.dpc); +p->set_privilege(STATE.dcsr.prv); + +/* We're not in Debug Mode anymore. */ +STATE.dcsr.cause = 0; |