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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-12 11:55:01 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-12 11:55:01 -0700 |
| commit | cc6e8787edd5112f3f4476b56022fffc98b2f3be (patch) | |
| tree | 6dea8df996c56b7d971bbd10ad312fe84ac48835 /riscv/insns/dret.h | |
| parent | ee3ef2b189227ee84b33ef69e5c7e9897fea6ba4 (diff) | |
| download | riscv-isa-sim-cc6e8787edd5112f3f4476b56022fffc98b2f3be.zip riscv-isa-sim-cc6e8787edd5112f3f4476b56022fffc98b2f3be.tar.gz riscv-isa-sim-cc6e8787edd5112f3f4476b56022fffc98b2f3be.tar.bz2 | |
Add debug_mode state bit, rather than overloading dcsr.cause
In the previous scheme, debug-mode software could exit debug mode by
zeroing the dcsr.cause field. While benign, that behavior is out of
spec.
Diffstat (limited to 'riscv/insns/dret.h')
| -rw-r--r-- | riscv/insns/dret.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h index 35c19cb..1a9dfe4 100644 --- a/riscv/insns/dret.h +++ b/riscv/insns/dret.h @@ -3,7 +3,7 @@ set_pc_and_serialize(STATE.dpc); p->set_privilege(STATE.dcsr.prv); /* We're not in Debug Mode anymore. */ -STATE.dcsr.cause = 0; +STATE.debug_mode = false; if (STATE.dcsr.step) STATE.single_step = STATE.STEP_STEPPING; |