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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-12 11:56:13 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-12 11:56:13 -0700 |
| commit | a21e1433ee8223cd4981e0f536bf4fafabe05e3c (patch) | |
| tree | b8b6d1b4f47d46d8140f21dd56caf50ab1b7df26 /riscv/insns/dret.h | |
| parent | cc6e8787edd5112f3f4476b56022fffc98b2f3be (diff) | |
| download | riscv-isa-sim-a21e1433ee8223cd4981e0f536bf4fafabe05e3c.zip riscv-isa-sim-a21e1433ee8223cd4981e0f536bf4fafabe05e3c.tar.gz riscv-isa-sim-a21e1433ee8223cd4981e0f536bf4fafabe05e3c.tar.bz2 | |
DRET should not be legal in M-mode
Diffstat (limited to 'riscv/insns/dret.h')
| -rw-r--r-- | riscv/insns/dret.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h index 1a9dfe4..ba503a0 100644 --- a/riscv/insns/dret.h +++ b/riscv/insns/dret.h @@ -1,4 +1,4 @@ -require_privilege(PRV_M); +require(STATE.debug_mode); set_pc_and_serialize(STATE.dpc); p->set_privilege(STATE.dcsr.prv); |