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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-17 14:00:58 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-17 15:27:42 -0700 |
commit | 5e1d0059353a4756740df709f85c35ee86138ad6 (patch) | |
tree | 5d7b128e83b1123bb8204d0136c748c1b78af327 /riscv/insns/dret.h | |
parent | eb19d1c1deabf9c8ca7d0f3958b2b6d797f100a9 (diff) | |
download | riscv-isa-sim-5e1d0059353a4756740df709f85c35ee86138ad6.zip riscv-isa-sim-5e1d0059353a4756740df709f85c35ee86138ad6.tar.gz riscv-isa-sim-5e1d0059353a4756740df709f85c35ee86138ad6.tar.bz2 |
Allow mstatus.MPP to store bad values; instead, validate on MRET
Either approach is legal, but this more closely matches Rocket.
Diffstat (limited to 'riscv/insns/dret.h')
-rw-r--r-- | riscv/insns/dret.h | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h index bef9ef2..35c19cb 100644 --- a/riscv/insns/dret.h +++ b/riscv/insns/dret.h @@ -1,9 +1,6 @@ require_privilege(PRV_M); set_pc_and_serialize(STATE.dpc); -/* The debug spec says we can't crash when prv is set to an invalid value. */ -if (p->validate_priv(STATE.dcsr.prv)) { - p->set_privilege(STATE.dcsr.prv); -} +p->set_privilege(STATE.dcsr.prv); /* We're not in Debug Mode anymore. */ STATE.dcsr.cause = 0; |