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| author | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-22 18:40:04 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-26 17:17:53 -0700 |
| commit | 1fe77945de9bacaf1e10f05b1dad4d115c552216 (patch) | |
| tree | 52c911002f7371a5569385eb6d2e39387050eb34 /riscv/insns/dret.h | |
| parent | bfcf4707b301230542816fd7bd71f89d57d3ef16 (diff) | |
| download | riscv-isa-sim-1fe77945de9bacaf1e10f05b1dad4d115c552216.zip riscv-isa-sim-1fe77945de9bacaf1e10f05b1dad4d115c552216.tar.gz riscv-isa-sim-1fe77945de9bacaf1e10f05b1dad4d115c552216.tar.bz2 | |
Convert dcsr to csr_t
Diffstat (limited to 'riscv/insns/dret.h')
| -rw-r--r-- | riscv/insns/dret.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h index 2b4c9cd..01a3992 100644 --- a/riscv/insns/dret.h +++ b/riscv/insns/dret.h @@ -1,9 +1,9 @@ require(STATE.debug_mode); set_pc_and_serialize(STATE.dpc->read()); -p->set_privilege(STATE.dcsr.prv); +p->set_privilege(STATE.dcsr->prv); /* We're not in Debug Mode anymore. */ STATE.debug_mode = false; -if (STATE.dcsr.step) +if (STATE.dcsr->step) STATE.single_step = STATE.STEP_STEPPING; |