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| author | YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> | 2022-11-22 05:52:40 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-11-21 13:52:40 -0800 |
| commit | 0e6c3960be2507287f1d4051c7eaa6ea561574a4 (patch) | |
| tree | eac47a7db6195639965552854ded48fbce46e18b /riscv/insns/dret.h | |
| parent | 425e858340459c9eb219e85a805b4d7011b42e46 (diff) | |
| download | riscv-isa-sim-0e6c3960be2507287f1d4051c7eaa6ea561574a4.zip riscv-isa-sim-0e6c3960be2507287f1d4051c7eaa6ea561574a4.tar.gz riscv-isa-sim-0e6c3960be2507287f1d4051c7eaa6ea561574a4.tar.bz2 | |
When resuming from debug mode, clear mstatus.MPRV if the new privilege mode is less than M-mode (#1149)
Diffstat (limited to 'riscv/insns/dret.h')
| -rw-r--r-- | riscv/insns/dret.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h index 01a3992..56ce25b 100644 --- a/riscv/insns/dret.h +++ b/riscv/insns/dret.h @@ -1,6 +1,8 @@ require(STATE.debug_mode); set_pc_and_serialize(STATE.dpc->read()); p->set_privilege(STATE.dcsr->prv); +if (STATE.prv < PRV_M) + STATE.mstatus->write(STATE.mstatus->read() & ~MSTATUS_MPRV); /* We're not in Debug Mode anymore. */ STATE.debug_mode = false; |