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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 22:55:07 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 23:05:58 +0800 |
| commit | ce34edb0eecec520d6d2cfec5bda57ca90a69f14 (patch) | |
| tree | f5f5da62f53bced28e38349a1b41983bb916dcfa /riscv/insns/blt.h | |
| parent | 2aaa89c0cf8fe0f45d284c0847f11d175eb82e03 (diff) | |
| download | riscv-isa-sim-ce34edb0eecec520d6d2cfec5bda57ca90a69f14.zip riscv-isa-sim-ce34edb0eecec520d6d2cfec5bda57ca90a69f14.tar.gz riscv-isa-sim-ce34edb0eecec520d6d2cfec5bda57ca90a69f14.tar.bz2 | |
Add space between if/while/switch and '('
Add space between ')' and '{'
Diffstat (limited to 'riscv/insns/blt.h')
| -rw-r--r-- | riscv/insns/blt.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/blt.h b/riscv/insns/blt.h index c54fb76..cad064b 100644 --- a/riscv/insns/blt.h +++ b/riscv/insns/blt.h @@ -1,2 +1,2 @@ -if(sreg_t(RS1) < sreg_t(RS2)) +if (sreg_t(RS1) < sreg_t(RS2)) set_pc(BRANCH_TARGET); |