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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-02 19:25:49 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-02 19:25:49 -0800 |
| commit | 9e012462f53113dc9ed00d7fbb89aeafeb9b89e9 (patch) | |
| tree | 6b0b8e42d770f5ea5a1e6188eabac803d51876d0 /riscv/extension.cc | |
| parent | 6642f8c745b320bdb7bab2470c62defb1b1bb9e2 (diff) | |
| download | riscv-isa-sim-9e012462f53113dc9ed00d7fbb89aeafeb9b89e9.zip riscv-isa-sim-9e012462f53113dc9ed00d7fbb89aeafeb9b89e9.tar.gz riscv-isa-sim-9e012462f53113dc9ed00d7fbb89aeafeb9b89e9.tar.bz2 | |
Fix interrupt delegation for coprocessors
Diffstat (limited to 'riscv/extension.cc')
| -rw-r--r-- | riscv/extension.cc | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/riscv/extension.cc b/riscv/extension.cc index 5321c42..a34dd80 100644 --- a/riscv/extension.cc +++ b/riscv/extension.cc @@ -14,12 +14,7 @@ void extension_t::illegal_instruction() void extension_t::raise_interrupt() { - reg_t prv = p->get_state()->prv; - reg_t mie = get_field(p->get_state()->mstatus, MSTATUS_MIE); - - if (prv < PRV_M || (prv == PRV_M && mie)) - p->raise_interrupt(IRQ_COP); - + p->take_interrupt((reg_t)1 << IRQ_COP); // must not return throw std::logic_error("a COP exception was posted, but interrupts are disabled!"); } |