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author | Anup Patel <anup@brainfault.org> | 2021-12-14 11:25:55 +0530 |
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committer | Anup Patel <anup@brainfault.org> | 2022-04-20 10:20:10 +0530 |
commit | 5a433081f4ce1a49ee83d1a81cf4922e7542a20c (patch) | |
tree | c99dfe8db908caf9319c905e5bba388b3206d43a /riscv/dts.h | |
parent | d5b1a65c0e3a0b6b46eb66d5d0284bf3a6cc1e0c (diff) | |
download | riscv-isa-sim-5a433081f4ce1a49ee83d1a81cf4922e7542a20c.zip riscv-isa-sim-5a433081f4ce1a49ee83d1a81cf4922e7542a20c.tar.gz riscv-isa-sim-5a433081f4ce1a49ee83d1a81cf4922e7542a20c.tar.bz2 |
Add PLIC emulation
We need an interrupt controller in Spike which will allow us to
emulate more real-world devices such as UART, VirtIO net, VirtIO
block, etc.
The RISC-V PLIC (or SiFive PLIC) is the commonly used interrupt
controller in existing RISC-V platforms so this patch adds PLIC
emulation for Spike.
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'riscv/dts.h')
-rw-r--r-- | riscv/dts.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/dts.h b/riscv/dts.h index 6208151..66add51 100644 --- a/riscv/dts.h +++ b/riscv/dts.h @@ -21,6 +21,8 @@ int fdt_get_next_subnode(void *fdt, int node); int fdt_parse_clint(void *fdt, reg_t *clint_addr, const char *compatible); +int fdt_parse_plic(void *fdt, reg_t *plic_addr, uint32_t *ndev, + const char *compatible); int fdt_parse_pmp_num(void *fdt, int cpu_offset, reg_t *pmp_num); int fdt_parse_pmp_alignment(void *fdt, int cpu_offset, reg_t *pmp_align); int fdt_parse_mmu_type(void *fdt, int cpu_offset, const char **mmu_type); |