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author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
commit | 68aeeb5500521ff52c216862f9a653b64191f3ad (patch) | |
tree | 407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/devices.h | |
parent | 191634d2854dfed448fc323195f9b65c305e2d77 (diff) | |
parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
download | riscv-isa-sim-68aeeb5500521ff52c216862f9a653b64191f3ad.zip riscv-isa-sim-68aeeb5500521ff52c216862f9a653b64191f3ad.tar.gz riscv-isa-sim-68aeeb5500521ff52c216862f9a653b64191f3ad.tar.bz2 |
Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/devices.h')
-rw-r--r-- | riscv/devices.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/devices.h b/riscv/devices.h index df7b289..bccda34 100644 --- a/riscv/devices.h +++ b/riscv/devices.h @@ -45,6 +45,7 @@ class mem_t : public abstract_device_t { bool store(reg_t addr, size_t len, const uint8_t* bytes) { return load_store(addr, len, const_cast<uint8_t*>(bytes), true); } char* contents(reg_t addr); reg_t size() { return sz; } + void dump(std::ostream& o); private: bool load_store(reg_t addr, size_t len, uint8_t* bytes, bool store); @@ -60,6 +61,8 @@ class clint_t : public abstract_device_t { bool store(reg_t addr, size_t len, const uint8_t* bytes); size_t size() { return CLINT_SIZE; } void increment(reg_t inc); + uint64_t get_mtimecmp(reg_t hartid) { return mtimecmp[hartid]; } + uint64_t get_mtime() { return mtime; } private: typedef uint64_t mtime_t; typedef uint64_t mtimecmp_t; |