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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-29 16:17:53 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-03-29 18:12:18 -0700 |
| commit | acd953afd2f52d64e2264c2c7c713dc0ad614406 (patch) | |
| tree | d92c638a0b7f16e24bf5c4f5e64c2350c3c54315 /fesvr | |
| parent | a346ad57a2144f3af0759605c9268711c8bd670b (diff) | |
| download | riscv-isa-sim-acd953afd2f52d64e2264c2c7c713dc0ad614406.zip riscv-isa-sim-acd953afd2f52d64e2264c2c7c713dc0ad614406.tar.gz riscv-isa-sim-acd953afd2f52d64e2264c2c7c713dc0ad614406.tar.bz2 | |
When enabling the debug module, poll til it's really enabled
Resolves #435
Diffstat (limited to 'fesvr')
| -rw-r--r-- | fesvr/dtm.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/fesvr/dtm.cc b/fesvr/dtm.cc index 6e4952f..993011d 100644 --- a/fesvr/dtm.cc +++ b/fesvr/dtm.cc @@ -560,6 +560,8 @@ void dtm_t::producer_thread() // Enable the debugger. write(DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE); + // Poll until the debugger agrees it's enabled. + while ((read(DMI_DMCONTROL) & DMI_DMCONTROL_DMACTIVE) == 0) ; // These are checked every time we run an abstract command. uint32_t abstractcs = read(DMI_ABSTRACTCS); |