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author | Chih-Min Chao <48193236+chihminchao@users.noreply.github.com> | 2021-08-28 12:59:15 +0800 |
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committer | GitHub <noreply@github.com> | 2021-08-27 21:59:15 -0700 |
commit | f1f3e375f23d9f6d09be47e533e101d3d97e648d (patch) | |
tree | 47277f5ae9112670740f7a74c9cf22dfa2c4d1bf /disasm | |
parent | ea5d76121bef5e3d54bbaba21cce75d0299c461e (diff) | |
download | riscv-isa-sim-f1f3e375f23d9f6d09be47e533e101d3d97e648d.zip riscv-isa-sim-f1f3e375f23d9f6d09be47e533e101d3d97e648d.tar.gz riscv-isa-sim-f1f3e375f23d9f6d09be47e533e101d3d97e648d.tar.bz2 |
disasm: hyp: add hypervisor instructions (#785)
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'disasm')
-rw-r--r-- | disasm/disasm.cc | 42 |
1 files changed, 35 insertions, 7 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index eac162b..4eb6970 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -29,7 +29,7 @@ struct : public arg_t { std::string to_string(insn_t insn) const { return std::string("(") + xpr_name[insn.rs1()] + ')'; } -} amo_address; +} base_only_address; struct : public arg_t { std::string to_string(insn_t insn) const { @@ -483,12 +483,17 @@ static void NOINLINE add_fstore_insn(disassembler_t* d, const char* name, uint32 static void NOINLINE add_xamo_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) { - d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs2, &amo_address})); + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs2, &base_only_address})); } static void NOINLINE add_xlr_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) { - d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &amo_address})); + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &base_only_address})); +} + +static void NOINLINE add_xst_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrs2, &base_only_address})); } static void NOINLINE add_btype_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) @@ -662,7 +667,8 @@ disassembler_t::disassembler_t(int xlen) #define DEFINE_XLOAD(code) add_xload_insn(this, #code, match_##code, mask_##code); #define DEFINE_XSTORE(code) add_xstore_insn(this, #code, match_##code, mask_##code); #define DEFINE_XAMO(code) add_xamo_insn(this, #code, match_##code, mask_##code); - #define DEFINE_XAMO_LR(code) add_xlr_insn(this, #code, match_##code, mask_##code); + #define DEFINE_XLOAD_BASE(code) add_xlr_insn(this, #code, match_##code, mask_##code); + #define DEFINE_XSTORE_BASE(code) add_xst_insn(this, #code, match_##code, mask_##code); #define DEFINE_FLOAD(code) add_fload_insn(this, #code, match_##code, mask_##code); #define DEFINE_FSTORE(code) add_fstore_insn(this, #code, match_##code, mask_##code); #define DEFINE_FRTYPE(code) add_frtype_insn(this, #code, match_##code, mask_##code); @@ -705,9 +711,9 @@ disassembler_t::disassembler_t(int xlen) DEFINE_XAMO(amominu_d) DEFINE_XAMO(amomaxu_d) - DEFINE_XAMO_LR(lr_w) + DEFINE_XLOAD_BASE(lr_w) DEFINE_XAMO(sc_w) - DEFINE_XAMO_LR(lr_d) + DEFINE_XLOAD_BASE(lr_d) DEFINE_XAMO(sc_d) DEFINE_FLOAD(flw) @@ -850,7 +856,6 @@ disassembler_t::disassembler_t(int xlen) add_insn(new disasm_insn_t("fence", match_fence, mask_fence, {&iorw})); DEFINE_NOARG(fence_i); DEFINE_SFENCE_TYPE(sfence_vma); - DEFINE_NOARG(sfence_w_inval); DEFINE_NOARG(sfence_inval_ir); DEFINE_SFENCE_TYPE(sinval_vma); @@ -1001,6 +1006,29 @@ disassembler_t::disassembler_t(int xlen) DEFINE_FX2TYPE(flt_q); DEFINE_FX2TYPE(fle_q); + + // ext-h + DEFINE_XLOAD_BASE(hlv_b) + DEFINE_XLOAD_BASE(hlv_bu) + DEFINE_XLOAD_BASE(hlv_h) + DEFINE_XLOAD_BASE(hlv_hu) + DEFINE_XLOAD_BASE(hlv_w) + DEFINE_XLOAD_BASE(hlv_wu) + DEFINE_XLOAD_BASE(hlv_d) + + DEFINE_XLOAD_BASE(hlvx_hu) + DEFINE_XLOAD_BASE(hlvx_wu) + + DEFINE_XSTORE_BASE(hsv_b) + DEFINE_XSTORE_BASE(hsv_h) + DEFINE_XSTORE_BASE(hsv_w) + DEFINE_XSTORE_BASE(hsv_d) + + DEFINE_SFENCE_TYPE(hfence_gvma); + DEFINE_SFENCE_TYPE(hfence_vvma); + + + // ext-c DISASM_INSN("c.ebreak", c_add, mask_rd | mask_rvc_rs2, {}); add_insn(new disasm_insn_t("ret", match_c_jr | match_rd_ra, mask_c_jr | mask_rd | mask_rvc_imm, {})); DISASM_INSN("c.jr", c_jr, mask_rvc_imm, {&rvc_rs1}); |