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| author | Tsukasa #01 (a4lg) <research_trasio@irq.a4lg.com> | 2021-12-18 04:28:37 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-12-17 11:28:37 -0800 |
| commit | f1ca8de7217e6c3bcfc8e93db54258bd117b2151 (patch) | |
| tree | 01c8b4ba39e0e00f16350052332f0b46cc7d639b /disasm | |
| parent | 6751b49ac173676c927143d6822910ac2d06a548 (diff) | |
| download | riscv-isa-sim-f1ca8de7217e6c3bcfc8e93db54258bd117b2151.zip riscv-isa-sim-f1ca8de7217e6c3bcfc8e93db54258bd117b2151.tar.gz riscv-isa-sim-f1ca8de7217e6c3bcfc8e93db54258bd117b2151.tar.bz2 | |
Add disassembler support for `unimp' (#886)
Now it disassembles 0x0000 (invalid encoding of c.addi4spn) as c.unimp
(RVC). Non-RVC variant of unimp pseudoinstruction (0xc0001073) is also
implemented.
Diffstat (limited to 'disasm')
| -rw-r--r-- | disasm/disasm.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 54fdb48..9e26f0f 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -676,6 +676,9 @@ disassembler_t::disassembler_t(int xlen) #define DEFINE_XFTYPE(code) add_xftype_insn(this, #code, match_##code, mask_##code); #define DEFINE_SFENCE_TYPE(code) add_sfence_insn(this, #code, match_##code, mask_##code); + add_insn(new disasm_insn_t("unimp", match_csrrw|(CSR_CYCLE<<20), 0xffffffff, {})); + add_insn(new disasm_insn_t("c.unimp", 0, 0xffff, {})); + DEFINE_XLOAD(lb) DEFINE_XLOAD(lbu) DEFINE_XLOAD(lh) |