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author | liweiwei <liweiwei@iscas.ac.cn> | 2021-12-27 11:39:58 +0800 |
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committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-01-30 11:33:06 +0800 |
commit | e566c454fa88bf770d66a88298deb6daf2d80031 (patch) | |
tree | fbdffd742bb5d273047e1d0f1102927a166836e0 /disasm | |
parent | e205ca655c12df1ae0f6f3105bc8a671b049f161 (diff) | |
download | riscv-isa-sim-e566c454fa88bf770d66a88298deb6daf2d80031.zip riscv-isa-sim-e566c454fa88bf770d66a88298deb6daf2d80031.tar.gz riscv-isa-sim-e566c454fa88bf770d66a88298deb6daf2d80031.tar.bz2 |
add disasm support for cmo instructions
Diffstat (limited to 'disasm')
-rw-r--r-- | disasm/disasm.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 1e39c70..57ae27b 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -1831,6 +1831,12 @@ disassembler_t::disassembler_t(int xlen) DEFINE_RTYPE(pktt32); } + // ext-cmo + DISASM_INSN("cbo.clean", cbo_clean, 0, {&xrs1}); + DISASM_INSN("cbo.flush", cbo_flush, 0, {&xrs1}); + DISASM_INSN("cbo.inval", cbo_inval, 0, {&xrs1}); + DISASM_INSN("cbo.zero", cbo_zero, 0, {&xrs1}); + add_unknown_insns(this); } |