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| author | Andrew Waterman <andrew@sifive.com> | 2021-12-29 16:05:34 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-12-29 16:05:34 -0800 |
| commit | 336a5813fd3f72d5081344466bcbd3275227dae7 (patch) | |
| tree | dda54ea3d7b6ccace028884f8d3fba56b618a9f5 /disasm | |
| parent | d750d6a92bac6423eb4d9a390cab5a6dfbff9f37 (diff) | |
| download | riscv-isa-sim-336a5813fd3f72d5081344466bcbd3275227dae7.zip riscv-isa-sim-336a5813fd3f72d5081344466bcbd3275227dae7.tar.gz riscv-isa-sim-336a5813fd3f72d5081344466bcbd3275227dae7.tar.bz2 | |
Disassemble Zbs instructions
Diffstat (limited to 'disasm')
| -rw-r--r-- | disasm/disasm.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 53f71fa..1e39c70 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -850,6 +850,15 @@ disassembler_t::disassembler_t(int xlen) DEFINE_RTYPE(xperm16); DEFINE_RTYPE(xperm32); + DEFINE_RTYPE(bclr); + DEFINE_RTYPE(binv); + DEFINE_RTYPE(bset); + DEFINE_RTYPE(bext); + DEFINE_ITYPE_SHIFT(bclri); + DEFINE_ITYPE_SHIFT(binvi); + DEFINE_ITYPE_SHIFT(bseti); + DEFINE_ITYPE_SHIFT(bexti); + DEFINE_R3TYPE(cmix); DEFINE_R3TYPE(fsr); DEFINE_R3TYPE(fsri); |