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author | Andrew Waterman <andrew@sifive.com> | 2022-05-12 15:28:47 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-05-12 15:28:47 -0700 |
commit | 2bf4c8c3dfe9ef7a454b33f70a4611c9118ce405 (patch) | |
tree | 3783c3d5d9b723b99224193f4830a437c50ccc9f /disasm | |
parent | 8ed65cdc51c78dc11fddee862f1c8ab932fad252 (diff) | |
download | riscv-isa-sim-2bf4c8c3dfe9ef7a454b33f70a4611c9118ce405.zip riscv-isa-sim-2bf4c8c3dfe9ef7a454b33f70a4611c9118ce405.tar.gz riscv-isa-sim-2bf4c8c3dfe9ef7a454b33f70a4611c9118ce405.tar.bz2 |
Add missing Q, H, and Svinval extensions to disassembler fallback
Diffstat (limited to 'disasm')
-rw-r--r-- | disasm/disasm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index d18f089..2fbc1fb 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -2101,7 +2101,7 @@ disassembler_t::disassembler_t(const isa_parser_t *isa) // next-highest priority: other instructions in same base ISA std::string fallback_isa_string = std::string("rv") + std::to_string(isa->get_max_xlen()) + - "gcv_zfh_zba_zbb_zbc_zbs_zkn_zkr_zks_xbitmanip"; + "gqchv_zfh_zba_zbb_zbc_zbs_zkn_zkr_zks_svinval_xbitmanip"; isa_parser_t fallback_isa(fallback_isa_string.c_str(), DEFAULT_PRIV); add_instructions(&fallback_isa); |