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| author | sven <zhongcy93@gmail.com> | 2021-12-16 18:27:26 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-12-16 02:27:26 -0800 |
| commit | d1f2019ec1b412503a23a77bc1939693260e1966 (patch) | |
| tree | a6663276ef089d85afeaf652501fd352affd8b8f /config.h.in | |
| parent | 0f30988e4d0e8daac893834b91979f7700bab481 (diff) | |
| download | riscv-isa-sim-d1f2019ec1b412503a23a77bc1939693260e1966.zip riscv-isa-sim-d1f2019ec1b412503a23a77bc1939693260e1966.tar.gz riscv-isa-sim-d1f2019ec1b412503a23a77bc1939693260e1966.tar.bz2 | |
TSR is read-only 0 when S-mode is not supported. (#890)
According the privileged spec, TSR is read-only 0 when S-mode is not supported. (https://github.com/riscv/riscv-isa-manual/blob/56515289e5999512fe578cdddf861b730d790018/src/machine.tex#L860-L861)
Diffstat (limited to 'config.h.in')
0 files changed, 0 insertions, 0 deletions