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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2023-06-05 10:25:57 -0700 |
|---|---|---|
| committer | Jerry Zhao <jerryz123@berkeley.edu> | 2023-06-20 12:23:47 -0700 |
| commit | b2ab751ce317929a179fdad06ad12bdcc2be42a7 (patch) | |
| tree | fa88ede732aeeb79a41c73436b722c8438670828 | |
| parent | b9275b7ce23937b6ba0345eb30ebb9c82dbd3c3f (diff) | |
| download | riscv-isa-sim-b2ab751ce317929a179fdad06ad12bdcc2be42a7.zip riscv-isa-sim-b2ab751ce317929a179fdad06ad12bdcc2be42a7.tar.gz riscv-isa-sim-b2ab751ce317929a179fdad06ad12bdcc2be42a7.tar.bz2 | |
sim_t: Add sim_t::get_intctrl
| -rw-r--r-- | riscv/sim.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 7f08ec1..1cb0658 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -52,6 +52,7 @@ public: } const char* get_dts() { return dts.c_str(); } processor_t* get_core(size_t i) { return procs.at(i); } + abstract_interrupt_controller_t* get_intctrl() const { assert(plic.get()); return plic.get(); } virtual const cfg_t &get_cfg() const override { return *cfg; } virtual const std::map<size_t, processor_t*>& get_harts() const override { return harts; } |