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| author | Andrew Waterman <andrew@sifive.com> | 2023-06-21 16:46:52 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-06-21 16:46:52 -0700 |
| commit | 71f5a8fd1b1185b7c15151f116aa3fef058bf210 (patch) | |
| tree | f225a4f76ec4731744b92f9b7357384685973124 | |
| parent | 85d7f869e9415876ced914bf7c79a4218b51d6e1 (diff) | |
| parent | 6023896b0a4d8bf101b210b155721d74a2a06b0c (diff) | |
| download | riscv-isa-sim-71f5a8fd1b1185b7c15151f116aa3fef058bf210.zip riscv-isa-sim-71f5a8fd1b1185b7c15151f116aa3fef058bf210.tar.gz riscv-isa-sim-71f5a8fd1b1185b7c15151f116aa3fef058bf210.tar.bz2 | |
Merge pull request #1338 from aap-sc/aap-sc/sb_read_write_fixup
fixup sb_write/sb_read to handle exceptions
| -rw-r--r-- | riscv/debug_module.cc | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 0f75c5e..f7163ef 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -310,7 +310,7 @@ void debug_module_t::sb_read() } else { sbcs.error = 3; } - } catch (trap_load_access_fault& t) { + } catch (const mem_trap_t& ) { sbcs.error = 2; } } @@ -319,17 +319,21 @@ void debug_module_t::sb_write() { reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0]; D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address)); - if (sbcs.sbaccess == 0 && config.max_sba_data_width >= 8) { - sim->debug_mmu->store<uint8_t>(address, sbdata[0]); - } else if (sbcs.sbaccess == 1 && config.max_sba_data_width >= 16) { - sim->debug_mmu->store<uint16_t>(address, sbdata[0]); - } else if (sbcs.sbaccess == 2 && config.max_sba_data_width >= 32) { - sim->debug_mmu->store<uint32_t>(address, sbdata[0]); - } else if (sbcs.sbaccess == 3 && config.max_sba_data_width >= 64) { - sim->debug_mmu->store<uint64_t>(address, - (((uint64_t) sbdata[1]) << 32) | sbdata[0]); - } else { - sbcs.error = 3; + try { + if (sbcs.sbaccess == 0 && config.max_sba_data_width >= 8) { + sim->debug_mmu->store<uint8_t>(address, sbdata[0]); + } else if (sbcs.sbaccess == 1 && config.max_sba_data_width >= 16) { + sim->debug_mmu->store<uint16_t>(address, sbdata[0]); + } else if (sbcs.sbaccess == 2 && config.max_sba_data_width >= 32) { + sim->debug_mmu->store<uint32_t>(address, sbdata[0]); + } else if (sbcs.sbaccess == 3 && config.max_sba_data_width >= 64) { + sim->debug_mmu->store<uint64_t>(address, + (((uint64_t) sbdata[1]) << 32) | sbdata[0]); + } else { + sbcs.error = 3; + } + } catch (const mem_trap_t& ) { + sbcs.error = 2; } } |