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| author | Andrew Waterman <andrew@sifive.com> | 2018-10-04 16:15:55 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-10-04 16:16:16 -0700 |
| commit | f54ff67b56592a28ce5b5ed729ceb6ad22f7cb8d (patch) | |
| tree | 588ae40deba9f85e8a82e7d35630549a195a8ba2 | |
| parent | 1d66556fcafd1661407466e22192df2ade1e609b (diff) | |
| download | riscv-isa-sim-f54ff67b56592a28ce5b5ed729ceb6ad22f7cb8d.zip riscv-isa-sim-f54ff67b56592a28ce5b5ed729ceb6ad22f7cb8d.tar.gz riscv-isa-sim-f54ff67b56592a28ce5b5ed729ceb6ad22f7cb8d.tar.bz2 | |
Set marchid to assigned value 5
https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md
TODO: allow Spike users to override marchid/mvendorid/mimpid to
mimic their hardware implementations more closely.
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index db2acd6..00612f0 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -662,7 +662,7 @@ reg_t processor_t::get_csr(int which) case CSR_MCAUSE: return state.mcause; case CSR_MTVAL: return state.mtval; case CSR_MISA: return state.misa; - case CSR_MARCHID: return 0; + case CSR_MARCHID: return 5; case CSR_MIMPID: return 0; case CSR_MVENDORID: return 0; case CSR_MHARTID: return id; |