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| author | Andrew Waterman <andrew@sifive.com> | 2018-08-21 14:24:23 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-08-21 14:25:53 -0700 |
| commit | b6ec196e9efe33d29d0c9fb80202737719c7730f (patch) | |
| tree | c2eb89e1843765f75c72c9039008799682a159e2 | |
| parent | 8a485de092c1ffc79105db34aca8875203921d63 (diff) | |
| download | riscv-isa-sim-b6ec196e9efe33d29d0c9fb80202737719c7730f.zip riscv-isa-sim-b6ec196e9efe33d29d0c9fb80202737719c7730f.tar.gz riscv-isa-sim-b6ec196e9efe33d29d0c9fb80202737719c7730f.tar.bz2 | |
Instantiate disassembler after max_xlen is known
This fixes RVC disassembly.
It's done in a way that doesn't break 2cd60b277e909a5599ca48e4561cbfbc61460186
| -rw-r--r-- | riscv/processor.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index ecbe3ef..8bcd8e2 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -24,12 +24,16 @@ processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id, : debug(false), halt_request(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset), last_pc(1), executions(1) { - disassembler = new disassembler_t(max_xlen); parse_isa_string(isa); register_base_instructions(); mmu = new mmu_t(sim, this); + disassembler = new disassembler_t(max_xlen); + if (ext) + for (auto disasm_insn : ext->get_disasms()) + disassembler->add_insn(disasm_insn); + reset(); } |