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author | Andrew Waterman <andrew@sifive.com> | 2018-09-27 13:51:01 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2018-09-27 13:51:13 -0700 |
commit | 84789691762b6dff4849b19f27005027edf77794 (patch) | |
tree | 83b49ea8b5f62156ebc6f6a7aed08466f58ae222 | |
parent | 606314955661d65ac080fc9a8ff198cfed8be1ad (diff) | |
download | riscv-isa-sim-84789691762b6dff4849b19f27005027edf77794.zip riscv-isa-sim-84789691762b6dff4849b19f27005027edf77794.tar.gz riscv-isa-sim-84789691762b6dff4849b19f27005027edf77794.tar.bz2 |
Add comment about CSR read side effects
-rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 88e1a63..db2acd6 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -557,6 +557,9 @@ void processor_t::set_csr(int which, reg_t val) } } +// Note that get_csr is sometimes called when read side-effects should not +// be actioned. In other words, Spike cannot currently support CSRs with +// side effects on reads. reg_t processor_t::get_csr(int which) { uint32_t ctr_en = -1; |