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| author | Andrew Waterman <andrew@sifive.com> | 2018-07-31 11:26:47 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-07-31 11:27:22 -0700 |
| commit | 1ff2a70ec87c0a418ca38cdff9b14fc29e4b1ecb (patch) | |
| tree | 05ab817cc83f3ba6fd38704ec19e803825548219 | |
| parent | 2cd60b277e909a5599ca48e4561cbfbc61460186 (diff) | |
| download | riscv-isa-sim-1ff2a70ec87c0a418ca38cdff9b14fc29e4b1ecb.zip riscv-isa-sim-1ff2a70ec87c0a418ca38cdff9b14fc29e4b1ecb.tar.gz riscv-isa-sim-1ff2a70ec87c0a418ca38cdff9b14fc29e4b1ecb.tar.bz2 | |
Make sstatus.MXR readable
h/t @taoliug
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 52f69c1..2a4a18c 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -584,7 +584,7 @@ reg_t processor_t::get_csr(int which) case CSR_MCOUNTEREN: return state.mcounteren; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS - | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL; + | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL; reg_t sstatus = state.mstatus & mask; if ((sstatus & SSTATUS_FS) == SSTATUS_FS || (sstatus & SSTATUS_XS) == SSTATUS_XS) |