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| author | Andrew Waterman <andrew@sifive.com> | 2018-10-03 12:13:55 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-10-03 12:13:55 -0700 |
| commit | 1d66556fcafd1661407466e22192df2ade1e609b (patch) | |
| tree | a2e5eca1d5f3e7cd20059d6f7fffdafddb0a2945 | |
| parent | 84789691762b6dff4849b19f27005027edf77794 (diff) | |
| download | riscv-isa-sim-1d66556fcafd1661407466e22192df2ade1e609b.zip riscv-isa-sim-1d66556fcafd1661407466e22192df2ade1e609b.tar.gz riscv-isa-sim-1d66556fcafd1661407466e22192df2ade1e609b.tar.bz2 | |
fix disassembly of c.addi4spn
Resolves #243
| -rw-r--r-- | spike_main/disasm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index bc1e41b..81264dd 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -568,7 +568,7 @@ disassembler_t::disassembler_t(int xlen) DISASM_INSN("c.jalr", c_jalr, mask_rvc_imm, {&rvc_rs1}); DISASM_INSN("c.nop", c_addi, mask_rd | mask_rvc_imm, {}); DISASM_INSN("c.addi16sp", c_addi16sp, mask_rd, {&rvc_sp, &rvc_addi16sp_imm}); - DISASM_INSN("c.addi4spn", c_addi4spn, 0, {&rvc_rs1s, &rvc_sp, &rvc_addi4spn_imm}); + DISASM_INSN("c.addi4spn", c_addi4spn, 0, {&rvc_rs2s, &rvc_sp, &rvc_addi4spn_imm}); DISASM_INSN("c.li", c_li, 0, {&xrd, &rvc_imm}); DISASM_INSN("c.lui", c_lui, 0, {&xrd, &rvc_uimm}); DISASM_INSN("c.addi", c_addi, 0, {&xrd, &rvc_imm}); |