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| author | Luís Marques <luis@luismarques.eu> | 2019-02-04 20:28:49 +0100 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2019-02-04 11:28:49 -0800 |
| commit | 1916b185e25f9e99f192633eadeac592d64d35c4 (patch) | |
| tree | a574c72a1e9105d4f8e9c295b46bb7b9ea24b477 | |
| parent | 2b38c82833addb35fd8aea0e63f8deeaa44a5a86 (diff) | |
| download | riscv-isa-sim-1916b185e25f9e99f192633eadeac592d64d35c4.zip riscv-isa-sim-1916b185e25f9e99f192633eadeac592d64d35c4.tar.gz riscv-isa-sim-1916b185e25f9e99f192633eadeac592d64d35c4.tar.bz2 | |
Fix use of old name `riscv-isa-run` (#269)
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 3d8ad78..08d5854 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -146,7 +146,7 @@ void processor_t::set_histogram(bool value) #ifndef RISCV_ENABLE_HISTOGRAM if (value) { fprintf(stderr, "PC Histogram support has not been properly enabled;"); - fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n"); + fprintf(stderr, " please re-build the riscv-isa-sim project using \"configure --enable-histogram\".\n"); } #endif } |