diff options
author | Tim Newsome <tim@sifive.com> | 2022-04-22 10:57:31 -0700 |
---|---|---|
committer | Tim Newsome <tim@sifive.com> | 2022-04-22 10:57:31 -0700 |
commit | f2f6037fea9313f43f7e94872304ab18ead0181d (patch) | |
tree | ccb093c91e45fa15fb5a7719699ff6f1adfb1986 | |
parent | 16413646bb44d8752c25f0f36745b6b74a2a1025 (diff) | |
download | riscv-isa-sim-f2f6037fea9313f43f7e94872304ab18ead0181d.zip riscv-isa-sim-f2f6037fea9313f43f7e94872304ab18ead0181d.tar.gz riscv-isa-sim-f2f6037fea9313f43f7e94872304ab18ead0181d.tar.bz2 |
Remove mcontrol_t.h
It was removed from the spec a long time ago.
-rw-r--r-- | riscv/triggers.cc | 4 | ||||
-rw-r--r-- | riscv/triggers.h | 1 |
2 files changed, 1 insertions, 4 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 99e3597..7f6be44 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -5,7 +5,7 @@ namespace triggers { mcontrol_t::mcontrol_t() : select(false), timing(false), chain_bit(false), - match(MATCH_EQUAL), m(false), h(false), s(false), u(false), + match(MATCH_EQUAL), m(false), s(false), u(false), execute_bit(false), store_bit(false), load_bit(false) { } @@ -22,7 +22,6 @@ reg_t mcontrol_t::tdata1_read(const processor_t * const proc) const noexcept { v = set_field(v, MCONTROL_CHAIN, chain_bit); v = set_field(v, MCONTROL_MATCH, match); v = set_field(v, MCONTROL_M, m); - v = set_field(v, MCONTROL_H, h); v = set_field(v, MCONTROL_S, s); v = set_field(v, MCONTROL_U, u); v = set_field(v, MCONTROL_EXECUTE, execute_bit); @@ -56,7 +55,6 @@ bool mcontrol_t::tdata1_write(processor_t * const proc, const reg_t val) noexcep break; } m = get_field(val, MCONTROL_M); - h = get_field(val, MCONTROL_H); s = get_field(val, MCONTROL_S); u = get_field(val, MCONTROL_U); execute_bit = get_field(val, MCONTROL_EXECUTE); diff --git a/riscv/triggers.h b/riscv/triggers.h index 1e74c91..75ee405 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -101,7 +101,6 @@ public: bool chain_bit; match_t match; bool m; - bool h; bool s; bool u; bool execute_bit; |