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| author | Pirmin Vogel <vogelpi@lowrisc.org> | 2022-05-16 12:10:09 +0200 |
|---|---|---|
| committer | Pirmin Vogel <vogelpi@lowrisc.org> | 2022-05-16 12:14:08 +0200 |
| commit | a59c44eb468ae366dbf2dc60c371b1c090e311cf (patch) | |
| tree | ce9341a7dc5440d23b0d28344ec8508db06a001b | |
| parent | e94d843e8b2772ec860258f006c8a3126a92a781 (diff) | |
| download | riscv-isa-sim-a59c44eb468ae366dbf2dc60c371b1c090e311cf.zip riscv-isa-sim-a59c44eb468ae366dbf2dc60c371b1c090e311cf.tar.gz riscv-isa-sim-a59c44eb468ae366dbf2dc60c371b1c090e311cf.tar.bz2 | |
Include recently added headers in riscv/riscv.mk.in
| -rw-r--r-- | riscv/riscv.mk.in | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 0c6b977..45fe2eb 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -13,9 +13,12 @@ riscv_hdrs = \ decode.h \ devices.h \ dts.h \ + isa_parser.h \ mmu.h \ cfg.h \ processor.h \ + p_ext_macros.h \ + v_ext_macros.h \ sim.h \ simif.h \ trap.h \ |