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| author | Andrew Waterman <andrew@sifive.com> | 2022-05-12 14:06:27 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-05-12 14:22:45 -0700 |
| commit | 68b20a9b8af4e9adbff9cccaef2b7c6b2c8ec190 (patch) | |
| tree | 62c47d77751aa00ba29e7c14a624868d9031af4c | |
| parent | 11f5942b7d8211e61b5ad9259d118033692c0759 (diff) | |
| download | riscv-isa-sim-68b20a9b8af4e9adbff9cccaef2b7c6b2c8ec190.zip riscv-isa-sim-68b20a9b8af4e9adbff9cccaef2b7c6b2c8ec190.tar.gz riscv-isa-sim-68b20a9b8af4e9adbff9cccaef2b7c6b2c8ec190.tar.bz2 | |
Remove insn_func_t::supported field
The field is rendered unnecessary by 11f5942b7d8211e61b5ad9259d118033692c0759.
Undoes some changes from 750f008e723bb3b20cec41a47ed5cec549447665.
| -rw-r--r-- | customext/cflush.cc | 6 | ||||
| -rw-r--r-- | riscv/processor.cc | 1 | ||||
| -rw-r--r-- | riscv/processor.h | 6 | ||||
| -rw-r--r-- | riscv/rocc.cc | 8 |
4 files changed, 8 insertions, 13 deletions
diff --git a/customext/cflush.cc b/customext/cflush.cc index 1a5cfa2..8b72a97 100644 --- a/customext/cflush.cc +++ b/customext/cflush.cc @@ -24,9 +24,9 @@ class cflush_t : public extension_t std::vector<insn_desc_t> get_instructions() { std::vector<insn_desc_t> insns; - insns.push_back((insn_desc_t){true, 0xFC000073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); - insns.push_back((insn_desc_t){true, 0xFC200073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); - insns.push_back((insn_desc_t){true, 0xFC100073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); + insns.push_back((insn_desc_t){0xFC000073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); + insns.push_back((insn_desc_t){0xFC200073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); + insns.push_back((insn_desc_t){0xFC100073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); return insns; } diff --git a/riscv/processor.cc b/riscv/processor.cc index dd61cae..2cc1003 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -961,7 +961,6 @@ void processor_t::register_base_instructions() extern reg_t rv64e_##name(processor_t*, insn_t, reg_t); \ if (name##_supported) { \ register_insn((insn_desc_t) { \ - name##_supported, \ name##_match, \ name##_mask, \ rv32i_##name, \ diff --git a/riscv/processor.h b/riscv/processor.h index 96fdc54..ec1b400 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -29,7 +29,6 @@ reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc); struct insn_desc_t { - bool supported; insn_bits_t match; insn_bits_t mask; insn_func_t rv32i; @@ -39,9 +38,6 @@ struct insn_desc_t insn_func_t func(int xlen, bool rve) { - if (!supported) - return NULL; - if (rve) return xlen == 64 ? rv64e : rv32e; else @@ -50,7 +46,7 @@ struct insn_desc_t static insn_desc_t illegal() { - return {true, 0, 0, &illegal_instruction, &illegal_instruction, &illegal_instruction, &illegal_instruction}; + return {0, 0, &illegal_instruction, &illegal_instruction, &illegal_instruction, &illegal_instruction}; } }; diff --git a/riscv/rocc.cc b/riscv/rocc.cc index 2d09095..f50934f 100644 --- a/riscv/rocc.cc +++ b/riscv/rocc.cc @@ -32,10 +32,10 @@ customX(3) std::vector<insn_desc_t> rocc_t::get_instructions() { std::vector<insn_desc_t> insns; - insns.push_back((insn_desc_t){true, 0x0b, 0x7f, &::illegal_instruction, c0, &::illegal_instruction, c0}); - insns.push_back((insn_desc_t){true, 0x2b, 0x7f, &::illegal_instruction, c1, &::illegal_instruction, c1}); - insns.push_back((insn_desc_t){true, 0x5b, 0x7f, &::illegal_instruction, c2, &::illegal_instruction, c2}); - insns.push_back((insn_desc_t){true, 0x7b, 0x7f, &::illegal_instruction, c3, &::illegal_instruction, c3}); + insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0, &::illegal_instruction, c0}); + insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, c1, &::illegal_instruction, c1}); + insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2, &::illegal_instruction, c2}); + insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3, &::illegal_instruction, c3}); return insns; } |