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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2022-05-11 02:37:24 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2022-05-11 08:56:54 -0700 |
| commit | 08afafccfd3ceaf6e158fc6a040bb0c931caa51b (patch) | |
| tree | 10d32f1af6d3d197c8e9ed0e324d39957d6e0976 | |
| parent | 3099c33d15281ff71bf5c9b7ec5a76f86df1ab60 (diff) | |
| download | riscv-isa-sim-08afafccfd3ceaf6e158fc6a040bb0c931caa51b.zip riscv-isa-sim-08afafccfd3ceaf6e158fc6a040bb0c931caa51b.tar.gz riscv-isa-sim-08afafccfd3ceaf6e158fc6a040bb0c931caa51b.tar.bz2 | |
rvv: fix the checking eew and elen for index load
eew of index register can't be larger than elen
ex:
elen = 32, vloxei64.v is illegal
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/v_ext_macros.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 2a32979..4df6813 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -84,6 +84,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) #define VI_CHECK_ST_INDEX(elt_width) \ require_vector(false); \ + require(elt_width <= P.VU.ELEN); \ float vemul = ((float)elt_width / P.VU.vsew * P.VU.vflmul); \ require(vemul >= 0.125 && vemul <= 8); \ reg_t emul = vemul < 1 ? 1 : vemul; \ |