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| author | marcfedorow <mark.fedorov@cloudbear.ru> | 2021-07-08 14:42:00 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-08 04:42:00 -0700 |
| commit | db6f5795270c922d52041fd016261982687dd145 (patch) | |
| tree | 218ce9a1e6c843195c83e143192f01e4bed078d8 | |
| parent | cc38be9991f3abd0831d141ebff8b4fd7a4990ea (diff) | |
| download | riscv-isa-sim-db6f5795270c922d52041fd016261982687dd145.zip riscv-isa-sim-db6f5795270c922d52041fd016261982687dd145.tar.gz riscv-isa-sim-db6f5795270c922d52041fd016261982687dd145.tar.bz2 | |
Sgn-extension for Krypto insns. (See: #682) (#739)
| -rw-r--r-- | riscv/insns/sha256sig0.h | 2 | ||||
| -rw-r--r-- | riscv/insns/sha256sig1.h | 2 | ||||
| -rw-r--r-- | riscv/insns/sha256sum0.h | 2 | ||||
| -rw-r--r-- | riscv/insns/sha256sum1.h | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/riscv/insns/sha256sig0.h b/riscv/insns/sha256sig0.h index b09e34a..b2820c3 100644 --- a/riscv/insns/sha256sig0.h +++ b/riscv/insns/sha256sig0.h @@ -6,7 +6,7 @@ require_extension('K'); uint32_t a = RS1; WRITE_RD( - ROR32(a, 7) ^ ROR32(a,18) ^ (a >> 3) + sext_xlen(ROR32(a, 7) ^ ROR32(a,18) ^ (a >> 3)) ); #undef ROR32 diff --git a/riscv/insns/sha256sig1.h b/riscv/insns/sha256sig1.h index b2118a0..2b853d5 100644 --- a/riscv/insns/sha256sig1.h +++ b/riscv/insns/sha256sig1.h @@ -6,7 +6,7 @@ require_extension('K'); uint32_t a = RS1; WRITE_RD( - ROR32(a, 17) ^ ROR32(a,19) ^ (a >> 10) + sext_xlen(ROR32(a, 17) ^ ROR32(a,19) ^ (a >> 10)) ); #undef ROR32 diff --git a/riscv/insns/sha256sum0.h b/riscv/insns/sha256sum0.h index 5c3048a..53f3485 100644 --- a/riscv/insns/sha256sum0.h +++ b/riscv/insns/sha256sum0.h @@ -6,7 +6,7 @@ require_extension('K'); uint32_t a = RS1; WRITE_RD( - ROR32(a, 2) ^ ROR32(a,13) ^ ROR32(a, 22) + sext_xlen(ROR32(a, 2) ^ ROR32(a,13) ^ ROR32(a, 22)) ); #undef ROR32 diff --git a/riscv/insns/sha256sum1.h b/riscv/insns/sha256sum1.h index 8724b4e..70d9226 100644 --- a/riscv/insns/sha256sum1.h +++ b/riscv/insns/sha256sum1.h @@ -6,7 +6,7 @@ require_extension('K'); uint32_t a = RS1; WRITE_RD( - ROR32(a, 6) ^ ROR32(a,11) ^ ROR32(a, 25) + sext_xlen(ROR32(a, 6) ^ ROR32(a,11) ^ ROR32(a, 25)) ); #undef ROR32 |