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| author | Jiuyang Liu <liu@jiuyang.me> | 2021-06-07 09:43:50 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-06 18:43:50 -0700 |
| commit | a21b6dd7aca9345a61f109c04f28b682dd0c67aa (patch) | |
| tree | 4b5fb456cf8a2ca8e62a63f7b4ca5c71ed13fe97 | |
| parent | 1621807a7c0dbd29f503377661a6b05930e8d365 (diff) | |
| download | riscv-isa-sim-a21b6dd7aca9345a61f109c04f28b682dd0c67aa.zip riscv-isa-sim-a21b6dd7aca9345a61f109c04f28b682dd0c67aa.tar.gz riscv-isa-sim-a21b6dd7aca9345a61f109c04f28b682dd0c67aa.tar.bz2 | |
fix typo. (#723)
| -rw-r--r-- | riscv/platform.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/platform.h b/riscv/platform.h index abe36c0..6618d44 100644 --- a/riscv/platform.h +++ b/riscv/platform.h @@ -1,6 +1,6 @@ // See LICENSE for license details. #ifndef _RISCV_PLATFORM_H -#define _RISCV_PLATFROM_H +#define _RISCV_PLATFORM_H #define DEFAULT_RSTVEC 0x00001000 #define CLINT_BASE 0x02000000 |