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author | Andrew Waterman <andrew@sifive.com> | 2021-06-04 02:25:32 -0700 |
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committer | GitHub <noreply@github.com> | 2021-06-04 02:25:32 -0700 |
commit | 7fa7a2007a8182593b1371375641d87c9da61312 (patch) | |
tree | 22f18ee458d58f036785d2726a1c2c13d4fc8560 | |
parent | bf4b1e09ed8e7a11ecff9891b12ce5d7f3375722 (diff) | |
parent | 9d91c7abe019c0e46f609508b5db1bbecf07dbf0 (diff) | |
download | riscv-isa-sim-7fa7a2007a8182593b1371375641d87c9da61312.zip riscv-isa-sim-7fa7a2007a8182593b1371375641d87c9da61312.tar.gz riscv-isa-sim-7fa7a2007a8182593b1371375641d87c9da61312.tar.bz2 |
Merge pull request #699 from chihminchao/misc-fix-2021-04-21
Misc fix 2021 04 21
-rw-r--r-- | disasm/disasm.cc | 3 | ||||
-rw-r--r-- | fesvr/htif.cc | 2 | ||||
-rw-r--r-- | riscv/devices.h | 1 | ||||
-rw-r--r-- | riscv/dts.cc | 1 | ||||
-rw-r--r-- | riscv/encoding.h | 8 | ||||
-rw-r--r-- | riscv/insns/mret.h | 2 | ||||
-rw-r--r-- | riscv/insns/sret.h | 2 | ||||
-rw-r--r-- | riscv/insns/vdot_vv.h | 5 | ||||
-rw-r--r-- | riscv/insns/vdotu_vv.h | 5 | ||||
-rw-r--r-- | riscv/insns/vfdot_vv.h | 11 | ||||
-rw-r--r-- | riscv/platform.h | 11 | ||||
-rw-r--r-- | riscv/processor.cc | 3 | ||||
-rw-r--r-- | riscv/riscv.mk.in | 3 | ||||
-rw-r--r-- | riscv/sim.cc | 1 | ||||
-rw-r--r-- | spike_main/spike.cc | 39 |
15 files changed, 41 insertions, 56 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 5741c43..1c26c43 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -1096,8 +1096,6 @@ disassembler_t::disassembler_t(int xlen) //0b11_0000 DISASM_OPIV_S___INSN(vwredsumu, 0); DISASM_OPIV_S___INSN(vwredsum, 1); - DISASM_OPIV_V___INSN(vdotu, 0); - DISASM_OPIV_V___INSN(vdot, 1); //OPMVV/OPMVX //0b00_0000 @@ -1307,7 +1305,6 @@ disassembler_t::disassembler_t(int xlen) DISASM_OPIV_WF_INSN(vfwadd); DISASM_OPIV_WF_INSN(vfwsub); DISASM_OPIV_VF_INSN(vfwmul); - DISASM_OPIV_V__INSN(vfdot); DISASM_OPIV_VF_INSN(vfwmacc); DISASM_OPIV_VF_INSN(vfwnmacc); DISASM_OPIV_VF_INSN(vfwmsac); diff --git a/fesvr/htif.cc b/fesvr/htif.cc index 4f34cec..1a9d0fc 100644 --- a/fesvr/htif.cc +++ b/fesvr/htif.cc @@ -3,7 +3,7 @@ #include "htif.h" #include "rfb.h" #include "elfloader.h" -#include "encoding.h" +#include "platform.h" #include "byteorder.h" #include <algorithm> #include <assert.h> diff --git a/riscv/devices.h b/riscv/devices.h index 187f220..9200f29 100644 --- a/riscv/devices.h +++ b/riscv/devices.h @@ -4,6 +4,7 @@ #include "decode.h" #include "mmio_plugin.h" #include "abstract_device.h" +#include "platform.h" #include <map> #include <vector> #include <utility> diff --git a/riscv/dts.cc b/riscv/dts.cc index 93e72f3..632dc57 100644 --- a/riscv/dts.cc +++ b/riscv/dts.cc @@ -2,6 +2,7 @@ #include "dts.h" #include "libfdt.h" +#include "platform.h" #include <iostream> #include <sstream> #include <signal.h> diff --git a/riscv/encoding.h b/riscv/encoding.h index 55088d6..7c02e14 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1,6 +1,6 @@ /* * This file is auto-generated by running 'make ../riscv-isa-sim/riscv/encoding.h' in - * https://github.com/riscv/riscv-opcodes (e8f0392) + * https://github.com/riscv/riscv-opcodes (7d1a0e3) */ /* See LICENSE for license details. */ @@ -211,12 +211,6 @@ #define IRQ_COP 12 #define IRQ_HOST 13 -#define DEFAULT_RSTVEC 0x00001000 -#define CLINT_BASE 0x02000000 -#define CLINT_SIZE 0x000c0000 -#define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 - /* page table entry (PTE) fields */ #define PTE_V 0x001 /* Valid */ #define PTE_R 0x002 /* Read */ diff --git a/riscv/insns/mret.h b/riscv/insns/mret.h index cedfc72..fd1d3a9 100644 --- a/riscv/insns/mret.h +++ b/riscv/insns/mret.h @@ -3,6 +3,8 @@ set_pc_and_serialize(p->get_state()->mepc); reg_t s = STATE.mstatus; reg_t prev_prv = get_field(s, MSTATUS_MPP); reg_t prev_virt = get_field(s, MSTATUS_MPV); +if (prev_prv != PRV_M) + s = set_field(s, MSTATUS_MPRV, 0); s = set_field(s, MSTATUS_MIE, get_field(s, MSTATUS_MPIE)); s = set_field(s, MSTATUS_MPIE, 1); s = set_field(s, MSTATUS_MPP, PRV_U); diff --git a/riscv/insns/sret.h b/riscv/insns/sret.h index 315f4f0..b940acd 100644 --- a/riscv/insns/sret.h +++ b/riscv/insns/sret.h @@ -9,6 +9,8 @@ reg_t next_pc = (STATE.v) ? p->get_state()->vsepc : p->get_state()->sepc; set_pc_and_serialize(next_pc); reg_t s = STATE.mstatus; reg_t prev_prv = get_field(s, MSTATUS_SPP); +if (prev_prv != PRV_M) + s = set_field(s, MSTATUS_MPRV, 0); s = set_field(s, MSTATUS_SIE, get_field(s, MSTATUS_SPIE)); s = set_field(s, MSTATUS_SPIE, 1); s = set_field(s, MSTATUS_SPP, PRV_U); diff --git a/riscv/insns/vdot_vv.h b/riscv/insns/vdot_vv.h deleted file mode 100644 index 7685230..0000000 --- a/riscv/insns/vdot_vv.h +++ /dev/null @@ -1,5 +0,0 @@ -// vdot vd, vs2, vs1 -VI_VV_LOOP -({ - vd += vs2 * vs1; -}) diff --git a/riscv/insns/vdotu_vv.h b/riscv/insns/vdotu_vv.h deleted file mode 100644 index 9c4c59d..0000000 --- a/riscv/insns/vdotu_vv.h +++ /dev/null @@ -1,5 +0,0 @@ -// vdotu vd, vs2, vs1 -VI_VV_ULOOP -({ - vd += vs2 * vs1; -}) diff --git a/riscv/insns/vfdot_vv.h b/riscv/insns/vfdot_vv.h deleted file mode 100644 index 8f5225a..0000000 --- a/riscv/insns/vfdot_vv.h +++ /dev/null @@ -1,11 +0,0 @@ -// vfdot.vv vd, vs2, vs1 -VI_VFP_VV_LOOP -({ - vd = f16_add(vd, f16_mul(vs2, vs1)); -}, -{ - vd = f32_add(vd, f32_mul(vs2, vs1)); -}, -{ - vd = f64_add(vd, f64_mul(vs2, vs1)); -}) diff --git a/riscv/platform.h b/riscv/platform.h new file mode 100644 index 0000000..abe36c0 --- /dev/null +++ b/riscv/platform.h @@ -0,0 +1,11 @@ +// See LICENSE for license details. +#ifndef _RISCV_PLATFORM_H +#define _RISCV_PLATFROM_H + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +#endif diff --git a/riscv/processor.cc b/riscv/processor.cc index b62f98a..9b6fe12 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -8,6 +8,7 @@ #include "simif.h" #include "mmu.h" #include "disasm.h" +#include "platform.h" #include <cinttypes> #include <cmath> #include <cstdlib> @@ -244,7 +245,7 @@ void processor_t::parse_isa_string(const char* str) p++; } else if (*p == 'x') { const char* ext = p + 1, *end = ext; - while (islower(*end) || *end == '_') + while (islower(*end)) end++; auto ext_str = std::string(ext, end - ext); diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 622d2ad..dffbd58 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -486,8 +486,6 @@ riscv_insn_ext_v_alu_int = \ vdiv_vx \ vdivu_vv \ vdivu_vx \ - vdot_vv \ - vdotu_vv \ vid_v \ viota_m \ vmacc_vv \ @@ -687,7 +685,6 @@ riscv_insn_ext_v_alu_fp = \ vfcvt_xu_f_v \ vfdiv_vf \ vfdiv_vv \ - vfdot_vv \ vfmacc_vf \ vfmacc_vv \ vfmadd_vf \ diff --git a/riscv/sim.cc b/riscv/sim.cc index e9e61c5..1418af4 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -5,6 +5,7 @@ #include "dts.h" #include "remote_bitbang.h" #include "byteorder.h" +#include "platform.h" #include <fstream> #include <map> #include <iostream> diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 4cbe971..50c4aa8 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -114,26 +114,25 @@ void merge_overlapping_memory_regions(std::vector<std::pair<reg_t, mem_t*>>& mem // check the user specified memory regions and merge the overlapping or // eliminate the containing parts std::sort(mems.begin(), mems.end(), sort_mem_region); - reg_t start_page = 0, end_page = 0; - std::vector<std::pair<reg_t, mem_t*>>::reverse_iterator it = mems.rbegin(); - std::vector<std::pair<reg_t, mem_t*>>::reverse_iterator _it = mems.rbegin(); - for(; it != mems.rend(); ++it) { - reg_t _start_page = it->first/PGSIZE; - reg_t _end_page = _start_page + it->second->size()/PGSIZE; - if (_start_page >= start_page && _end_page <= end_page) { - // contains - mems.erase(std::next(it).base()); - }else if ( _start_page < start_page && _end_page > start_page) { - // overlapping - _it->first = _start_page; - if (_end_page > end_page) - end_page = _end_page; - mems.erase(std::next(it).base()); - }else { - _it = it; - start_page = _start_page; - end_page = _end_page; - assert(start_page < end_page); + std::vector<std::pair<reg_t, mem_t*>>::iterator it = mems.begin() + 1; + + while (it != mems.end()) { + reg_t start = prev(it)->first; + reg_t end = prev(it)->first + prev(it)->second->size(); + reg_t start2 = it->first; + reg_t end2 = it->first + it->second->size(); + + //contains -> remove + if (start2 >= start && end2 <= end) { + it = mems.erase(it); + //parital overlapped -> extend + } else if (start2 >= start && start2 < end) { + delete prev(it)->second; + prev(it)->second = new mem_t(std::max(end, end2) - start); + it = mems.erase(it); + // no overlapping -> keep it + } else { + it++; } } } |